The present invention relates to the adjustment of the dot clock in a matrix display device such as a liquid-crystal panel, digital micromirror device (DMD), plasma display panel (PDP), or field-emission display (FED).
These devices commonly use an analog-to-digital converter (ADC) to convert an analog image signal to the digital the signal needed for a matrix display. The dot clock is the sampling clock of the ADC. Before the display of the image begins, the dot clock must be adjusted in frequency and phase so that the analog image signal will be sampled at the correct points. Various methods of performing these adjustments automatically are known.
For example, Japanese Unexamined Patent Application No. 11-175033 discloses the liquid crystal display device shown in FIG. 1, having an ADC 101, a phase-locked loop (PLL) 102, a clock phase automatic adjusting means 103, a counter 104, an image detector 105, a pulse generator 106, and a control means 107. The ADC 101 receives an analog image signal that includes image information interspersed with vertical and horizontal blanking intervals. The image detector 105 detects the starting and ending points of the image information in the digitized image signal output from the ADC 101. The control means 107 sets the frequency division ratio of the PLL 102 according to the difference between the starting and ending points, so that the displayed image will have the same width as the screen of the liquid crystal display (LCD, not visible). The PLL 102 locks the frequency of the dot clock (DCLK) at the set ratio in relation to an input horizontal synchronizing signal (HSYNC).
After the dot-clock frequency has been adjusted in this way, the clock phase automatic adjusting means 103 detects the phase difference between the image signal and the dot clock, and generates a voltage that increases with this difference. The control means 107 uses this voltage signal to adjust the phase of the dot clock so that transition points in the image-signal waveform coincide with transition points in the dot-clock waveform. After the phase adjustment, the image detector 105 again detects the start of the image, and the control means 107 uses the result to control the pulse generator 106 so that each horizontal line of the displayed image starts at the left edge of the display screen.
A problem with this method is that it assumes that the image is always intended to fill the entire width of the display screen. The adjustment fails when this assumption is false, as when an image with a black border is displayed.
As another example of the prior art, Japanese Unexamined Patent Application No. 11-177847 discloses a device that automatically adjusts the frequency and phase of the dot clock so as to maximize the absolute difference between the values of adjacent pixels.
To explain this method, FIG. 2 shows an image comprising a pattern of high-contrast vertical stripes, displayed with the correct dot-clock frequency and phase. FIG. 3 shows the same image displayed with the correct frequency but incorrect phase; the stripes appear faint and low in contrast. The absolute difference between adjacent pixel values at the edges of the stripes is lower in FIG. 3 than in FIG. 2. The dot-clock phase is adjusted by varying the phase until the maximum absolute difference is obtained.
FIG. 4 shows the same image displayed with the incorrect dot-clock frequency; the stripes now vary periodically between high and low contrast. The average absolute difference between adjacent pixel values is less than in FIG. 2. The dot-clock frequency is adjusted by varying the frequency division ratio of the PLL until the average absolute difference is maximized.
One problem with this method is illustrated in FIG. 5, which shows the same image displayed at the same incorrect dot-clock frequency as in FIG. 4, but with a different dot-clock phase. The stripes vary between high and low contrast with the same period as before, but the high- and low-contrast stripes now appear in different positions. FIG. 5 happens to have more low-contrast stripes than FIG. 4, so the average absolute difference between adjacent pixel values is lower in FIG. 5 than in FIG. 4, even though the dot-clock frequency is the same in both cases.
There are also cases (not illustrated) in which different dot-clock frequencies produce the same average absolute difference, or in which the average absolute difference increases as the dot-clock frequency moves away from the correct frequency. Adjusting the dot-clock frequency according to the average absolute difference between adjacent pixel values thus turns out to be an uncertain process, and the adjustment does not necessarily succeed unless all possible frequencies are tested one by one, a very time-consuming operation.